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IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
INDUSTRIAL TEMPERATURE RANGE
3.2
POWER-ON SEQUENCE
To power on the IDT821054, users should follow the sequence
below:
1. Apply ground first;
2. Apply VCC, finish signal connections and set the RESET pin to logic
low. The device then goes into the default state;
3. Set the RESET pin to logic high;
4. Select master clock frequency;
5. Program filter coefficients and other parameters as required;
3.3
DEFAULT STATE AFTER RESET
When the IDT821054 is powered on, or reset either by command or
by setting the RESET pin to logic low for at least 50 s, the device will
enter the default state as follows:
1. All four channels are powered down and in standby mode.
2. All loopbacks and cutoff are disabled.
3. The DX1 pin is selected for all channels to transmit data and the DR1
pin is selected for all channels to receive data.
4. The master clock frequency is 2.048 MHz.
5. Transmit and receive time slots are set to be 0-3 respectively for
Channel 1-4. The PCM data rate is as same as the BCLK frequency.
The PCM data is transmitted on rising edges of the BCLK signal and
received on falling edges of it.
6. A-Law is selected.
7. The digital filters including GRX, FRR, GTX, FRX, GIS, ECF and IMF
are disabled. The high-pass filters (HPF) are enabled. Refer to
Figure - 4 and descriptions on LREG1 for details.
8. The SB1, SB2 and SB3 pins are configured as inputs.
9. The SI1 and SI2 pins are configured as no debounce.
10.All interrupts are disabled and all pending interrupts are cleared.
11. All feature function blocks including FSK generator, dual tone
generators, hardware ring trip and level meter are disabled.
12.The outputs of CHCLK1 and CHCLK2 are set to high.
The data stored in the RAM will not be changed by any kind of reset
operations. So the RAM data will not be lost unless the device is
powered down physically.
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